How to build a useful thousand-core manycore system?

Current hardware roadmaps call for doubling the number of on-chip cores approximately every two years. If this trend materializes, in at most a decade and a half, we will reach one thousand cores. This scenario has mind-boggling consequences for the IPDPS research community. There are many questions to answer. For example, at the architecture level, how are we going to power these chips and provide the required bandwidth? At the software level, how are we going to manage possiblyheterogeneous resources with low overhead, efficiently compile for these machines, and provide programmer-friendly programming models? At the application level, what kinds of applications and algorithms will we use? This panel will provide an opportunity for the conference attendees to discuss all of these topics. Bio: Josep Torrellas (http://iacoma.cs.uiuc.edu) is a Professor of Computer Science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. Prior to joining Illinois, Torrellas received a PhD in Electrical Engineering from Stanford University in 1992. He also spent a sabbatical year at IBM’s T.J. Watson Research Center. Torrellas’s research area is multiprocessor computer architecture. He has made extensive contributions in the areas of shared-memory multiprocessor organization, speculative multithreading, hardware reliability and variability, support for software dependability, and integration of processors and memory. He has participated in the Stanford DASH and the Illinois Cedar experimental multiprocessor projects. He leads the I-ACOMA Multiprocessor project, where he is designing the Bulk Multicore Architecture, a novel architecture focused on enhancing programmability. He has published over 150 papers in computer architecture. Torrellas is an IEEE Fellow. He received an NSF Young Investigator Award, an IBM Partnership Award, and many best-paper awards. He has graduated 25 PhD students, some of whom are now leaders in academia and industry.